As semiconductor devices have become more highly integrated, the distance between interconnections is reduced. Due to the high dielectric constant of the material used for insulating interconnections from each other, parasitic capacitance between the interconnections is increased, causing signal delays, and degrading the characteristics of the device.
As the size of semiconductor devices is reduced, the thickness of the inter metal dielectric (IMD) layer for separating metals from each other is reduced. As a result, interference and cross-talk occurs between upper and lower metal layers.
When the interlayer dielectric layer has a high dielectric constant, a larger parasitic capacitance is formed between the IMD layer and the upper and lower metal layers. For this reason, various new materials and new processing methods have been studied to reduce the dielectric constant between the metal layers.
Also, as semiconductor devices have become more highly integrated, even the vias that connect metal interconnections are also more tightly integrated. Therefore, the defects of the semiconductor device increase, which becomes a critical matter to be solved in the process of manufacturing the semiconductor device.
When the metal layers are positioned on the integrated vias, during a subsequent thermal process, the moisture included in the vias is evaporated and causes stress to the metal layers and thus generates problems such as voids or blisters in the metal layers.